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USB2250/51/59
Ultra Fast USB 2.0 Multi-Format Flash Media Controller
PRODUCT FEATURES
General Description
The SMSC USB2250/51/59 is a USB 2.0 compliant, high speed Mass Storage Class Peripheral Controller intended for reading and writing to more than 24 popular flash media formats from the CompactFlash(R) (CF), SmartMediaTM (SM), xD Picture CardTM (xD)1, Memory StickTM (MS), Secure Digital (SD), and MultiMediaCardTM (MMC) families. The SMSC USB2250/51/59 is a fully integrated, single chip solution capable of ultra high performance operation. Average sustained transfer rates exceeding 35MB/s are possible if the media and host can support those rates. GPIO configuration and polarity
-- Up to 11 GPIOs (based on configuration) for special function use: LED indicators, button inputs, power control to memory devices, etc. -- Four GPIO's with up to 200 mA drive. -- An additional 16 GPIO's if CF is not used.
Datasheet
On Board 24MHz Crystal Driver Circuit Optional external 24MHz clock input 4 Independent Internal Card Power FETs
-- 200mA each -- "Fold-back" short circuit current protected
8051 8-bit microprocessor
-- 60MHz - single cycle execution -- 64KB ROM2; 14KB RAM
General Features 128-pin VTQFP lead-free RoHS compliant package
Targeted for applications in which single or "combo" media sockets are used. Supports multiple simultaneous card insertions Flexible assignment of number of LUNs and how card types are associated with the LUNs Hardware-controlled data flow architecture for all selfmapped media Pipelined hardware support for access to non-selfmapped media
Hardware Features
Single Chip Flash Media Controller with non-multiplexed interface for independent card sockets Flash Media Specification Revision Compliance
-- Compact Flash Specification 4.1 -- Memory Stick Specification 1.43 -- Memory Stick Pro Format Specification 1.02 -- Memory Stick Pro-HG Duo Format Specification 1.01 -- xD Picture Card 1.2 -- Smart Media Specification 1.3 -- Secure Digital 2.0
- - Memory Stick, MS Duo, HS-MS, MS Pro-HG, MS Pro - - CF UDMA Modes 0-4 CF PIO Modes 0-6
Internal Regulator for 1.8V core operation Optimized pinout improves signal routing, easing implementation and allowing for improved signal integrity. OEM Selectable Features VID/PID/Language ID 28-character Manufacturer ID and Product string 12-hex digit (max) Serial Number string Customizable Vendor specific data by optional use of external serial EEPROM Bus- or Self-powered selection LED blink interval or duration Internal power FET configuration
Software Features
Optimized for low latency interrupt handling Reduced memory footprint Device Firmware Upgrade (DFU) support of external EEPROM or External Flash
-- Assembly line support -- End user field upgrade support -- DFU Package consists of driver, firmware, sample DFU application and source code, DFU driver API
-- MultiMediaCard Specification 4.2
- 1/4/8 bit MMC
HS-SD, HC-SD, TransFlashTM and reduced form factor media
Optional (Mandatory on the USB2259) custom firmware with external ROM (up to 128k) Please see the USB2250/USB2251 Software Release Notes for additional Software Features
SDIO and MMC Streaming Mode support Extended configuration options
-- xD player mode operation -- Socket switch polarities, etc.
Applications
Media Activity LED
Flash Media Card Reader/Writer Printers Desktop and Mobile PCs Consumer A/V Media Players/Viewers Vista ReadyBoostTM
1.) xD Picture Card not applicable to USB2251
2.USB2259 uses external ROM only, internal ROM unavailable
SMSC USB2250/51/59
DATASHEET
Revision 2.6 (05-08-08)
Ultra Fast USB 2.0 Multi-Format Flash Media Controller Datasheet
ORDER NUMBER: USB2250/51/59-NU-XX for 128 pin, VTQFP Lead-Free RoHS Compliant Package
Note: "XX" does not apply to the USB2259 because there is no ROM.
"XX" in the order number indicates the internal ROM firmware revision level. Please contact your SMSC sales representative for more information.
Table 0.1 USB2250/51/59 Comparison of Features
CompactFlash(R) Memory StickTM MultiMediaCardTM Secure Digital SmartMediaTM
ROM USB2250
xD Picture CardTM
. .
External Only
. . .
. .
USB2251
USB2259
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
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Table of Contents
Chapter 1 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chapter 2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 3 Pin Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 3.2 128-Pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 128-Pin List. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 5.2 USB2250/51/59 128-Pin VTQFP Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chapter 6 Pin Reset State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1 128-Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Chapter 7 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1 7.2 7.3 7.4 Maximum Guaranteed Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 30 31 33
Chapter 8 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8.1 Oscillator/Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 10 GPIO Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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List of Figures
Figure 2.1 Figure 2.2 Figure 4.1 Figure 6.1 Figure 6.2 Figure 7.1 Figure 8.1 Figure 8.2 Figure 9.1 USB2250/2251 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 USB2259 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 USB2250/51/59 128-Pin VTQFP Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Legend for Pin Reset States Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Supply Rise Time Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Typical Crystal Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Formula to Find Value of C1 and C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 USB2250/51/59 128-Pin VTQFP, 14x14x1.0mm Body, 2.0mm Pitch . . . . . . . . . . . . . . . . . . 35
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List of Tables
Table 0.1 USB2250/51/59 Comparison of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 3.1 USB2250/51/59 128-Pin VTQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3.2 USB2250/51/59 128-Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 5.2 USB2250/51/59 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 6.1 USB2250/51/59 128-Pin Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table 7.1 Pin Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 10.1 USB2250/51/59 GPIO Usage (ROM Rev 0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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Chapter 1 Acronyms
SM: SmartMedia SMC: SmartMedia Controller CF: Compact Flash CFC: CompactFlash Controller SD: Secure Digital SDC: Secure Digital Controller MMC: MultiMediaCard MS: Memory Stick MSC: Memory Stick Controller xD: xD Picture Card
*Note: In order to develop, make, use, or sell readers and/or other products using or incorporating any of the SMSC devices made the subject of this document or to use related SMSC software programs, technical information and licenses under patent and other intellectual property rights from or through various persons or entities, including without limitation media standard companies, forums, and associations, and other patent holders may be required. These media standard companies, forums, and associations include without limitation the following: Sony Corporation (Memory Stick, Memory Stick Pro); SD3 LLC (Secure Digital); MultiMedia Card Association (MultiMediaCard); the SSFDC Forum (SmartMedia); the Compact Flash Association (Compact Flash); and Fuji Photo Film Co., Ltd., Olympus Optical Co., Ltd., and Toshiba Corporation (xD-Picture Card). SMSC does not make such licenses or technical information available; does not promise or represent that any such licenses or technical information will actually be obtainable from or through the various persons or entities (including the media standard companies, forums, and associations), or with respect to the terms under which they may be made available; and is not responsible for the accuracy or sufficiency of, or otherwise with respect to, any such technical information. SMSC's obligations (if any) under the Terms of Sale Agreement, or any other agreement with any customer, or otherwise, with respect to infringement, including without limitation any obligations to defend or settle claims, to reimburse for costs, or to pay damages, shall not apply to any of the devices made the subject of this document or any software programs related to any of such devices, or to any combinations involving any of them, with respect to infringement or claimed infringement of any existing or future patents related to solid state disk or other flash memory technology or applications ("Solid State Disk Patents"). By making any purchase of any of the devices made the subject of this document, the customer represents, warrants, and agrees that it has obtained all necessary licenses under then-existing Solid State Disk Patents for the manufacture, use and sale of solid state disk and other flash memory products and that the customer will timely obtain at no cost or expense to SMSC all necessary licenses under Solid State Disk Patents; that the manufacture and testing by or for SMSC of the units of any of the devices made the subject of this document which may be sold to the customer, and any sale by SMSC of such units to the customer, are valid exercises of the customer's rights and licenses under such Solid State Disk Patents; that SMSC shall have no obligation for royalties or otherwise under any Solid State Disk Patents by reason of any such manufacture, use, or sale of such units; and that SMSC shall have no obligation for any costs or expenses related to the customer's obtaining or having obtained rights or licenses under any Solid State Disk Patents. SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE. No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark, copyright, mask work right, trade secret, or other intellectual property right. **To obtain this software program the appropriate SMSC Software License Agreement must be executed and in effect. Forms of these Software License Agreements may be obtained by contacting SMSC.
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Chapter 2 Block Diagram
AUTO_ CBW PROC
SD/ MMC
USB Host
CF/ GPIO (16)
PHY
SIE CTL
BUS INTFC
BUS INTFC
FMDU CTL
FMI
MS
SM
EP0 TX EP0 RX BUS INTFC RAM
4K total
1.8V Reg
EP1 RX EP1 TX EP2 RX EP2 TX
XDATA BRIDGE + BUS ARBITER
PWR_FET0 PWR_FET1 PWR_FET2 PWR_FET3 GPIO8/CARD_PWR0 GPIO9/CARD_PWR1 GPIO10/CARD_PWR2 GPIO11/CARD_PWR3
PLL
GPIOs RAM 10KB ROM 64KB* Clock Generation and Control
8051 PROCESSOR SFR RAM
11 pins
ADDR MAP
Program Memory I/O Bus
*ROM is not available in USB2259
Figure 2.1 USB2250/2251 Block Diagram
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AUTO_ CBW PROC
SD/ MMC
USB Host
CF/ GPIO (16)
PHY
SIE CTL
BUS INTFC
BUS INTFC
FMDU CTL
FMI
MS
SM
EP0 TX EP0 RX BUS INTFC RAM
4K total
1.8V Reg
EP1 RX EP1 TX EP2 RX EP2 TX
XDATA BRIDGE + BUS ARBITER
PWR_FET0 PWR_FET1 PWR_FET2 PWR_FET3 GPIO8/CARD_PWR0 GPIO9/CARD_PWR1 GPIO10/CARD_PWR2 GPIO11/CARD_PWR3
PLL
GPIOs
11 pins
RAM 10KB
ADDR MAP
Program Memory I/O Bus
Clock Generation and Control
8051 PROCESSOR SFR RAM
Figure 2.2 USB2259 Block Diagram
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Chapter 3 Pin Table
3.1 128-Pin Package
Table 3.1 USB2250/51/59 128-Pin VTQFP Package COMPACTFLASH INTERFACE (28 PINS) CF_D0/GPIO16 CF_D4/GPIO20 CF_D8/GPIO24 CF_D12/GPIO28 CF_nIOR CF_IORDY CF_SA1 CF_D1/GPIO17 CF_D5/GPIO21 CF_D9/GPIO25 CF_D13/GPIO29 CF_nIOW CF_nCS0 CF_SA2 CF_D2/GPIO18 CF_D6/GPIO22 CF_D10/GPIO26 CF_D14/GPIO30 CF_IRQ CF_DMACK/GPIO7/TXD GPIO13 (CF_nCD) CF_D3/GPIO19 CF_D7/GPIO23 CF_D11/GPIO27 CF_D15/GPIO31 CF_nRESET CF_SA0 CF_DMARQ/GPIO2/RXD
SMARTMEDIA INTERFACE (17 PINS) SM_D0 SM_D4 SM_ALE SM_nWP SM_nWPS MEMORY STICK INTERFACE (11 PINS) MS_BS MS_D1 MS_D5 MS_D0/MS_SDIO MS_D2 MS_D6 MS_SCLK MS_D3 MS_D7 GPIO12 (MS_INS) MS_D4 SM_D1 SM_D5 SM_CLE SM_nB/R SM_D2 SM_D6 SM_nRE SM_nCE SM_D3 SM_D7 SM_nWE GPIO14 (SM_nCD)
SD/MMC INTERFACE (12 PINS) SD_CMD SD_D2 SD_D4 SD_CLK SD_D3 SD_D5 SD_D0 GPIO6 (SD_WP) SD_D6 SD_D1 GPIO15 (SD_nCD) SD_D7
USB INTERFACE (8 PINS) USB+ VDDA33 USBXTAL2 RBIAS XTAL1/CLKIN VDD18PLL REG_EN
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Table 3.1 USB2250/51/59 128-Pin VTQFP Package (continued) MEMORY/IO INTERFACE (28 PINS) MA0/CLK_SEL0 MA4 MA8 MA12 MA16 MD3 MD7 MA1/CLK_SEL1 MA5 MA9 MA13 MD0 MD4 nMRD MISC (10 PINS) nRESET GPIO1 (LED1) GPIO11/CARD_PWR3 GPIO3 (VBUS_DET) GPIO8/CARD_PWR0 TEST DIGITAL, POWER (14 PINS) (5) VDD33 (1) VDD18 TOTAL 128 (8) VSS GPIO4 (SCL/xD_ID) GPIO9/CARD_PWR1 GPIO5 (SDA) GPIO10/CARD_PWR2 MA2 MA6 MA10 MA14 MD1 MD5 nMWR MA3 MA7 MA11 MA15 MD2 MD6 nMCE
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3.2
PIN # 1 2 3 4 5 6 7 8 9 10 11 12
128-Pin List
Table 3.2 USB2250/51/59 128-Pin List PIN # 33 34 35 36 37 38 39 40 41 42 43 44 PIN # 65 66 67 68 69 70 71 72 73 74 75 76 PIN # 97 98 99 100 101 102 103 104 105 106 107 108
NAME MA12 MA15 nMWR MA14 GPIO5 (SDA) REG_EN USB+ USBVSS SD_D1 SD_D6 SD_D0
MA 12 12 12 12 12 12 12 12 12
NAME MD7 MD3 MD2 MD1 MD0 SM_nWPS SM_D7 SM_D6 SM_D5 SM_D4 SM_D3 SD_D2
MA 12 12 12 12 12 12 12 12 12 12 12
NAME VDD33 CF_D13 / GPIO29 CF_D6 / GPIO22 CF_D14 / GPIO30 CF_D7 / GPIO23 CF_D15 / GPIO31 CF_nCS0 CF_nIOR CF_nIOW CF_IRQ VSS GPIO10 / CRD_ PWR2 VDD33 GPIO9 / CRD_ PWR1 CF_nRESET CF_IORDY
MA 12 12 12 12 12 12 12 12 12 12
NAME MS_D6 GPIO12 (MS_INS) MS_D3 MS_D7 MS_SCLK VSS TEST VDD33 GPIO6 (SD_WP) MA7 MA13 MA6
MA 12 12 12 12 12 12 12 12 12
13 14
SD_D7 GPIO8 / CRD_ PWR0 VDD33 GPIO11 / CRD_ PWR3 VSS SD_CLK SD_D5 SD_CMD SD_D4
12 12
45 46
SM_D1 SM_D0
12 12
77 78
12
109 110
MA8 MA5
12 12
15 16
12
47 48
SM_nWP SM_nWE
12 12
79 80
12 12
111 112
MA9 MA4
12 12
17 18 19 20 21
12 12 12 12
49 50 51 52 53
VDD18 VDD33 VSS SM_ALE SM_CLE
12 12
81 82 83 84 85
VSS CF_SA2 CF_SA1 CF_SA0 CF_D0 / GPIO16 CF_D1 / GPIO17
12 12 12
113 114 115 116 117
MA11 MA3 nMRD MA2 CF_DMARQ / RXD / GPIO2 GPIO4 (SCL)
12 12 12 12 12
22
SD_D3
12
54
SM_nCE
12
86
12
118
12
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Table 3.2 USB2250/51/59 128-Pin List (continued) PIN # 23 PIN # 55 PIN # 87 PIN # 119
NAME SD_D2
MA 12
NAME SM_nRE
MA 12
NAME CF_D8 / GPIO24 CF_D2 / GPIO18 CF_D9 / GPIO25 CF_D10 / GPIO26 MS_BS
MA 12
NAME CF_DMACK / TXD / GPIO7 LED1 / GPIO1
GPIO3 (VBUS_DET)
MA 12
24 25
MA10 MA1 / CLK_ SEL1 nMCE MA0 / CLK_ SEL0 MA16 MD6 MD5 MD4 GPIO15 (SD_nCD)
12 12
56 57
SM_nB/R GPIO14 (SM_nCD) GPIO13 (CF_nCD) CF_D3 / GPIO19 CF_D11 / GPIO27 CF_D4 / GPIO20 CF_D12 / GPIO28 CF_D5 / GPIO21 nRESET
12
88 89
12 12
120 121
12 12
26 27
12 12
58 59
12 12
90 91
12 12
122 123
VSS XTAL2
-
28 29 30 31 32
12 12 12 12 12
60 61 62 63 64
12 12 12 12 -
92 93 94 95 96
MS_D1 MS_D5 MS_D0 / MS_DIO MS_D4 MS_D2
12 12 12 12 12
124 125 126 127 128
XTAL1 / CLKIN VDDPLL18 VSS RBIAS VDDA33
-
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Chapter 4 Pin Configuration
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
MS_D6 GPIO12 (MS_INS) MS_D3 MS_D7 MS_SCLK VSS TEST VDD33 GPIO6 (SD_WP) MA7 MA13 MA6 MA8 MA5 MA9 MA4 MA11 MA3 nMRD MA2 CF_DMARQ / RXD / GPIO2 GPIO4 (SCL) CF_DMACK / TXD / GPIO7 LED1 / GPIO1 GPIO3 (VBUS_DET) VSS XTAL2 XTAL1 (CLKIN) VDD18PLL VSS RBIAS VDDA33
65
MS_D2 MS_D4 MS_D0 / MS_SDIO MS_D5 MS_D1 MS_BS CF_D10 / GPIO26 CF_D9 / GPIO25 CF_D2 / GPIO18 CF_D8 / GPIO24 CF_D1 / GPIO17 CF_D0 / GPIO16 CF_SA0 CF_SA1 CF_SA2 VSS CF_IORDY CF_nRESET GPIO9 / CRD_PWR1 VDD33 GPIO10 / CRD_PWR2 VSS CF_IRQ CF_nIOW CF_nIOR CF_nCS0 CF_D15 / GPIO31 CF_D7 / GPIO23 CF_D14 / GPIO30 CF_D6 / GPIO22 CF_D13 / GPIO29 VDD33
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SMSC USB225X 128 VTQFP
(Top View)
nRESET CF_D5 / GPIO21 CF_D12 / GPIO28 CF_D4 / GPIO20 CF_D11 / GPIO27 CF_D3 / GPIO19 GPIO13 (CF_nCD) GPIO14 (SM_nCD) SM_nB/R SM_nRE SM_nCE SM_CLE SM_ALE VSS VDD33 VDD18 SM_nWE SM_nWP SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6 SM_D7 SM_nWPS MD0 MD1 MD2 MD3 MD7
10
11
12
13
14
15
16
17
18
19
20
21
22
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MA12 MA15 nMWR MA14 GPIO5 (SDA) REG_EN USB+ USBVSS SD_D1 SD_D6 SD_D0 SD_D7 GPIO8 / CRD_PWR0 VDD33 GPIO11 / CRD_PWR3 VSS SD_CLK SD_D5 SD_CMD SD_D4 SD_D3 SD_D2 MA10 MA1 / CLK_SEL1 nMCE MA0 / CLK_SEL0 MA16 MD6 MD5 MD4 GPIO15 (SD_nCD)
Figure 4.1 USB2250/51/59 128-Pin VTQFP Diagram
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Chapter 5 Pin Descriptions
This section provides a detailed description of each signal. The signals are arranged in functional groups according to their associated interface. The "n" symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage level. When "n" is not present before the signal name, the signal is asserted at the high voltage level. The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of "active low" and "active high" signals. The term assert, or assertion, indicates that a signal is active, independent of whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inactive.
5.1
USB2250/51/59 128-Pin VTQFP Pin Descriptions
Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions 128-PIN VTQFP BUFFER TYPE
NAME
SYMBOL
DESCRIPTION
COMPACT FLASH INTERFACE CF Chip Select 0 CF Register Address CF Interrupt CF_nCS0 71 O12 This pin is the active low chip select 0 signal for the task file registers of CF ATA device in the True IDE mode. These pins are the register select address bits for the CF ATA device. This is the active high interrupt request signal from the CF device. This pin has an internal weak pull-down resistor that can be controlled by: CF_INTF_EN bit of CFC_ATA_MODE_CTL CF Data 15-8 / GPIO CF_D[15:8] / GPIO[31:24] 70 68 66 62 60 90 89 87 I/O12PD CF_D[15:8]: The bi-directional data signals CF_D15 - CF_D8 in True IDE mode data transfer. In the True IDE Mode, all of task file register operations occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. The bi-directional data signal has an internal weak pull-down resistor. I/O12 GPIO[31:24]: These Pins are GPIOs if CF_INTF_EN bit of CFC_ATA_MODE CTL is disabled and EXTENDED_GPIO bit is set in UTIL_CONFIG1 is enabled.
CF_SA[2:0]
82 83 84 74
I/O12
CF_IRQ
IPD
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Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions (continued) 128-PIN VTQFP 69 67 63 61 59 88 86 85 BUFFER TYPE I/O12PD
NAME CF Data 7-0 / GPIO
SYMBOL CF_D[7:0] / GPIO[23:16]
DESCRIPTION CF_D[7:0]: The bi-directional data signals CF_D7 - CF_D0 in the True IDE mode data transfer. In the True IDE Mode, all of the task file register operations occur on the CF_D[7:0], while the data transfer is on CF_D[15:0]. The bi-directional data signal has an internal weak pull-down resistor.
I/O12
GPIO[23:16]: These Pins are GPIOs if CF_INTF_EN bit of CFC_ATA_MODE CTL is disabled and EXTENDED_GPIO bit is set in UTIL_CONFIG1 is enabled. This pin is active high input signal for IORDY. This pin has an internal weak pull-up resistor that can be controlled by: CF_INTF_EN bit of CFC_ATA_MODE CTL
IO Ready
CF_IORDY
80
IPU
CF Card Detection1 CF Hardware Reset CF IO Read CF IO Write Strobe CF DMA request
CF_nCD (GPIO13) CF_nRESET CF_nIOR CF_nIOW CF_DMARQ / GPIO2 / RXD
58 79 72 73 117
I/O12 O12 O12 O12 I I/O12 I
This is a GPIO designated as the Compact Flash card detection pin. This pin is an active low hardware reset signal to CF device. This pin is an active low read strobe signal for CF device. This pin is an active low write strobe signal for CF device. CF_DMARQ: This pin is the DMA request from the device to the CF controller. GPIO: This pin may be used either as input, edge sensitive interrupt input, or output. RXD: The signal can be used as input to the RXD of UART in the device, when the TXD_RXD_SEL bit in UTIL_CONFIG1 register is cleared to "0". CF_nDMACK: This pin is an active low dma acknowledge signal for CF device. GPIO: This pin may be used either as input, edge sensitive interrupt input, or output. TXD: In addition, as an output, the GPIO7 can be used as an output TXD of UART in the device, when the GPIO2/TXD bit in UTL_CONFIG register is set to "1"
CF DMA acknowledge
CF_nDMACK/ GPIO / TXD
119
O12 I/O12 O12
SMART MEDIA INTERFACE SM Write Protect SM_nWP 47 O12PD This pin is an active low write protect signal for the SM device. This pin has a weak pull-down resistor that is permanently enabled.
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Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions (continued) 128-PIN VTQFP 52 BUFFER TYPE O12PD
NAME SM Address Strobe
SYMBOL SM_ALE
DESCRIPTION This pin is an active high Address Latch Enable signal for the SM device. This pin has a weak pull-down resistor that is permanently enabled.
SM Command Strobe
SM_CLE
53
O12PD
This pin is an active high Command Latch Enable signal for the SM device. This pin has a weak pull-down resistor that is permanently enabled.
SM Data 7-0
SM_D[7:0]
39 40 41 42 43 44 45 46 55
I/O12PD
These pins are the bi-directional data signals SM_D7-SM_D0. The bi-directional data signal has an internal weak pull-down resistor.
SM Read Enable
SM_nRE
O12PU
This pin is an active low read strobe signal for SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET, and is controlled by the SM_PU bit of the SMC_CTL register. If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pull-ups must be used).
SM Write Enable
SM_nWE
48
O12PU
This pin is an active low write strobe signal for SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET, and is controlled by the SM_PU bit of the SMC_CTL register. If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pull-ups must be used).
SM Write Protect Switch
SM_nWPS
38
IPU
A write-protect seal is detected when this pin is low. This pin has an internal weak pull-up resistor that is controlled by the SM_INTF_EN bit of the SMC_MODE_CTL2 register.
SM Busy or Data Ready
SM_nBR
56
IPU
This pin is connected to the BSY/RDY pin of the SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET, and is controlled by the SM_PU bit of the SMC_CTL register. If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pull-ups must be used).
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Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions (continued) 128-PIN VTQFP 54 BUFFER TYPE O12PU
NAME SM Chip Enable
SYMBOL SM_nCE
DESCRIPTION This pin is the active low chip enable signal to the SM device. When using the internal FET, this pin has an internal weak pull-up resistor that is tied to the output of the internal Power FET, and is controlled by the SM_PU bit of the SMC_CTL register. If an external FET is used (Internal FET is disabled), then the internal pull-up is not available (external pull-ups must be used).
SM Card Detection GPIO
SM_nCD (GPIO14)
57
I/O12
This is a GPIO designated as the Smart Media card detection pin.
MEMORY STICK INTERFACE MS Bus State MS_BS 91 O12 This pin is connected to the BS pin of the MS device. It is used to control the Bus States 0, 1, 2 and 3 (BS0, BS1, BS2 and BS3) of the MS device. MS Card Insertion GPIO MS System CLK MS_INS (GPIO12) MS_SCLK 98 101 IPU O12 This is a GPIO designated as the Memory Stick card detection pin. This pin is an output clock signal to the MS device. The clock frequency is software configurable. MS System Data In/Out MS_D[7:1] 100 97 93 95 99 96 92 94 I/O12PD MS_D[7:0]: These pins are the bi-directional data signal for the MS device. MS_D2 and MS_D3 have weak pull-down resistors. MS_D1 has a pull down resistor if in parallel mode, otherwise it is disabled. In 4 or 8 bit parallel mode, there is a weak pull-down resistor on all MS_D7~0 signals. The resistors are controlled by MSC_SYSTEM_0, MSC_MODE_CTL and MSC_PRO_HG registers. MS_D0: This pin is one of the bi-directional data signals for the MS device. In serial mode, the most significant bit (MSB) of each byte is transmitted first by either MSC or MS device on MS_D0. MS_D0, MS_D2, and MS_D3 have weak pull-down resistors. MS_D1 has a pull down resistor if in parallel mode, otherwise it is disabled. In 4 or 8 bit parallel mode, there is a weak pulldown resistor on all MS_D7~0 signals. The resistors are controlled by MSC_SYSTEM_0, MSC_MODE_CTL and MSC_PRO_HG registers. MS_SDIO: Serial Data Bus. Transfer direction and types of data change depending on the Bus State.
MS System Data In/Out
MS_D0 / MS_SDIO
I/O12PD
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Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions (continued) 128-PIN VTQFP BUFFER TYPE
NAME
SYMBOL
DESCRIPTION
SD / MMC INTERFACE SD Data 7-0 SD_D[7:0] 13 11 19 21 22 23 10 12 18 I/O12PU These are the bi-directional data signals SD_D0 - SD_D7. The bi-directional signals should have weak pullup resistors. The register can be controlled by: SD_MMC_INTF_EN bit of SDC_MODE_CTL O12 This is an output clock signal to SD/MMC device. The clock frequency is software configurable. SD Command SD_CMD 20 I/O12PU This is a bi-directional signal that connects to the CMD signal of SD/MMC device. The bi-directional signal should have an internal weak pull-up resistor. The pull-up register can be controlled by: SD_MMC_INTF_EN bit of SDC_MODE CTL This is a GPIO designated as the Secure Digital card mechanical write detect pin. This is a GPIO designated as the Secure Digital card detection pin.
SD Clock
SD_CLK
SD Write Protected GPIO SD Card Detect GPIO
GPIO6 (SD_WP) GPIO15 (SD_nCD)
105
I/O12
32
I/O12
USB INTERFACE USB Bus Data USB Transceiver Bias Crystal Input/External Clock Input USB+ USBRBIAS 7 8 127 I/O-U I-R These pins connect to the USB bus data signals. A 12.0k , 1.0% resistor is attached from VSSA to this pin in order to set the transceiver's internal bias currents. 24MHz Crystal or external clock input. XTAL: This pin can be connected to one terminal of the crystal or can be connected to an external 24/48MHz clock when a crystal is not used. Note: The MA[1:0] pins will be sampled while nRESET is asserted, and the value will be latched upon nRESET negation. This will determine the clock source and value.
XTAL1 (CLKIN)
124
ICLKx
Crystal Output
XTAL2
123
OCLKx
24MHz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit.
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Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions (continued) 128-PIN VTQFP BUFFER TYPE
NAME
SYMBOL
DESCRIPTION
MEMORY / IO INTERFACE Memory Data Bus MD[7:0] 33 29 30 31 34 35 36 37 28 I/O12 These signals are used to transfer data between the internal CPU and the external program memory. Note: These pins have internal weak pull-up resistors that are controlled by the MD_PU_DIS bit of the PWR_MGMT_CTL1 register.
Memory Address Bus Memory Address Bus
MA16
O12
These signals address memory locations within the external memory. MA16 is a bit generated by the ROM Mapper. These signals address memory locations within the external memory. Note: USB2259 requires that MA2 be tied to 3.3V via a 10K resistor.
MA[15:2]
2 4 107 1 113 24 111 109 106 108 110 112 114 116 25 27
O12
Memory Address Bus
MA1[1:0] / CLK_ SEL1[1:0]
O12 I/O12PD
MA[1:0]: These signals address memory locations within the external memory. CLK_SEL[1:0]: During nRESET assertion, these pins will select the operating frequency of the external clock, and the corresponding weak pulldown resistors are enabled. When nRESET is negated, the value on these pins will be internal latched and these pins will revert to MA[1:0] functionality; the internal pull-downs will be disabled. CLK_SEL[1:0] CLK_SEL[1:0] CLK_SEL[1:0] CLK_SEL[1:0] Note: = = = = '00'. 24MHz '01'. RESERVED '10'. RESERVED '11'. 48MHz
If the latched value is '1', then the corresponding MA pin is tri-stated when the chip is in the powerdown state.
If the latched value is '0', then the corresponding MA pin will function identically to the MA[15:3] pins at all times (other than during nRESET assertion). Memory Write Strobe Memory Read Strobe
SMSC USB2250/51/59
nMWR nMRD
3 115
O12 O12
Program Memory Write; active low Program Memory Read; active low
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Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions (continued) 128-PIN VTQFP 26 BUFFER TYPE O12
NAME Memory Chip Enable
SYMBOL nMCE
DESCRIPTION Program Memory Chip Enable; active low. This signal is asserted when any external access is being done by the processor. This signal is held to logic 'high' while nRESET is asserted.
MISC General Purpose I/O LED1 / GPIO1 120 I/O12 This pin may be used either as input, edge sensitive interrupt input, or output. In addition, as an output, the GPIO1 can be used output controlled by the LED1_GPIO1 register. General Purpose I/O GPIO3 (VBUS_DET) 121 I/O12 This pin may be used either as input, edge sensitive interrupt input, or output. This pin is not 5V tolerant. An external resistor divider must be used when connected to VBUS. General Purpose I/O GPIO4 (SCL) 118 I/O12 O12 General Purpose I/O GPIO5 (SDA) 5 I/O12 This pin may be used either as input, edge sensitive interrupt input, or output. SCL: This is the clock output when used with an external EEPROM. This pin may be used either as input, edge sensitive interrupt input, or output. SDA: This is the data pin when used with an external serial EEPROM. General Purpose I/O GPIO8 / CRD_PWR0 14 I/O12 I/O200 General Purpose I/O GPIO9 / CRD_PWR1 78 I/O12 I/O200 General Purpose I/O GPIO10 / CRD_PWR2 76 I/O12 GPIO: This pin may be used either as input, edge sensitive interrupt input, or output. CRD_PWR: Card Power drive of 3.3V @ either 100mA or 200mA. GPIO: This pin may be used either as input, edge sensitive interrupt input, or output. CRD_PWR: Card Power drive of 3.3V @ either 100mA or 200mA. GPIO: These pins may be used either as input, edge sensitive interrupt input, or output. It is a requirement that this is the only FET used to power SM devices. Failure to do this will violate SM voltage specification on SM device pins. CRD_PWR: Card Power drive of 3.3V @ either 100mA or 200mA. GPIO: These pins may be used either as input, edge sensitive interrupt input, or output. CRD_PWR: Card Power drive of 3.3V @ either 100mA or 200mA.
I/O200 General Purpose I/O GPIO11 / CRD_PWR3 16 I/O12 I/O200
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Table 5.1 USB2250/51/59 128-Pin VTQFP Pin Descriptions (continued) 128-PIN VTQFP 64 BUFFER TYPE IS
NAME RESET Input
SYMBOL nRESET
DESCRIPTION This active low signal is used by the system to reset the chip. The active low pulse should be at least 1s wide. This signal is used for testing the chip. User should normally tie this pin low externally, if the test function is not used. This signal is used to enable the internal 1.8V regulator.
TEST Input
TEST
103
I
Regulator Enable
REG_EN
6
IPU
ANALOG / DIGITAL POWER, and GROUND 1.8V Digital Core Power VDD18 49 All VDD18 pins must be connected together on the circuit board. +1.8V Core power. If the internal regulator is enabled, then this pin must have a 1.0F (or greater) 20% (ESR <0.1) capacitor to VSS. 3.3V Power & Voltage Regulator Input 1.8V PLL Power VDD33 15 50 65 77 104 125 3.3V Power & Voltage Regulator Input
VDD18PLL
This pin is the 1.8V Power for the PLL. If the internal regulator is enabled, then this pin must have a 1.0F (or greater) 20% (ESR <0.1) capacitor to VSS.
3.3V Analog Power Ground
VDDA33 VSS
128 9 17 51 75 81 102 122 126
3.3V Analog Power Ground Reference
Notes: 1. Hot-insertion capable card connectors are required for all flash media. It is required for the SD connector to have a Write Protect switch. This allows the chip to detect the MMC card. 2. nMCE is normally asserted except when the 8051 is in standby mode. 3. Refer to PWR_MGMT_CTL1 register for controlling pull-up / down resistors associated with the pins as well as the individual card control registers.
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5.2
Buffer Type Descriptions
Table 5.2 USB2250/51/59 Buffer Type Descriptions BUFFER DESCRIPTION Input. Input with internal weak pull-up resistor. Input with internal weak pull-down resistor. Input with Schmitt trigger. Input/Output buffer with 12mA sink and 12mA source. Input/Output buffer 12mA with FET disabled, 100/200mA source only with FET enabled. Input/Output buffer with 12mA sink and 12mA source, with an internal weak pull-down resistor. Input/Output buffer with 12mA sink and 12mA source with a pull-up resistor. Output buffer with 12mA source. Output buffer with 12mA sink and 12mA source, with a pull-up resistor. Output buffer with 12mA sink and 12mA source, with a pull-down resistor. XTAL clock input. XTAL clock output. Analog Input/Output Defined in USB specification. RBIAS.
I IPU IPD IS I/O12 I/O200 I/O12PD I/O12PU O12 O12PU O12PD ICLKx OCLKx I/O-U I-R
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Chapter 6 Pin Reset State Table
Hardware Initialization
Voltage Signal (v)
Firmware Operational
RESET
VDD33
RESET
VSS
Time (t)
Figure 6.1 Pin Reset States
LEGEND yes -z pu pd hw (fw) VDD none
hardware enables function hardware disables function hardware disables output driver hardware enables pullup hardware enables pulldown hardware controls function, but state is protocol dependent firmware controls function through registers hardware supplies power through pin, applicable only to CARD_PWR pins hardware disables pad
Figure 6.2 Legend for Pin Reset States Table
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128-Pin Reset States
Table 6.1 USB2250/51/59 128-Pin Reset States
RESET STATE Post-Reset State xD Mode INPUT FUNCTION OUTPUT PU/ PD INPUT Post-Reset State SD Mode FUNCTION OUTPUT PU/ PD INPUT Post-Reset State MS Mode FUNCTION OUTPUT PU/ PD INPUT
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PIN
PIN NAME
FUNCTION
OUTPUT
PU/ PD
85 86 88 59 61 63 67 69 87 89 90 60 62 66 68 70 72
CF_D0/GPIO16 CF_D1/GPIO17 CF_D2/GPIO18 CF_D3/GPIO19 CF_D4/GPIO20 CF_D5/GPIO21 CF_D6/GPIO22 CF_D7/GPIO23 CF_D8/GPIO24 CF_D9/GPIO25 CF_D10/GPIO26 CF_D11/GPIO27 CF_D12/GPIO28 CF_D13/GPIO29 CF_D14/GPIO30 CF_D15/GPIO31 CF_nIOR
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO CF
z z z z z z z z z z z z z z z z z
------------------
------------------
CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF CF
hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw
pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd pd --
hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw --
GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO
(fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw)
(fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw)
(fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw) (fw)
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RESET STATE PIN PIN NAME FUNCTION OUTPUT PU/ PD INPUT
Post-Reset State xD Mode FUNCTION OUTPUT PU/ PD INPUT
Post-Reset State SD Mode FUNCTION OUTPUT PU/ PD INPUT
Post-Reset State MS Mode FUNCTION OUTPUT PU/ PD INPUT
73 74 79 80 71 84 83 82 119 117 58 46 45 44 43 42 41 40
CF_nIOW CF_nIRQ CF_nRESET CF_IORDY CF_nCS0 CF_SA0 CF_SA1 CF_SA2 CF_DMACK/GPIO7/TXD CF_DMARQ/GPIO2/RXD GPIO13(CF_nCD) SM_D0 SM_D1 SM_D2 SM_D3 SM_D4 SM_D5 SM_D6
CF CF CF CF CF CF CF CF GPIO GPIO GPIO SM SM SM SM SM SM SM
z z z z z z z z 0 0 z z z z z z z z
----------pu pd pd pd pd pd pd pd
----------yes --------
CF CF CF CF CF CF CF CF CF CF GPIO SM SM SM SM SM SM SM
hw z (fw) z hw hw hw hw hw z (fw) hw hw hw hw hw hw hw
-pd -pu (fw) ----pd (fw) pd pd pd pd pd pd pd
-yes -yes -----yes (fw) yes yes yes yes yes yes yes GPIO GPIO (fw) (fw) (fw) (fw) (fw) (fw) TXD RXD hw z -(fw) -yes
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Table 6.1 USB2250/51/59 128-Pin Reset States (continued)
Ultra Fast USB 2.0 Multi-Format Flash Media Controller Datasheet
Table 6.1 USB2250/51/59 128-Pin Reset States (continued)
RESET STATE PIN NAME FUNCTION OUTPUT PU/ PD INPUT Post-Reset State xD Mode FUNCTION OUTPUT PU/ PD INPUT Post-Reset State SD Mode FUNCTION OUTPUT PU/ PD INPUT Post-Reset State MS Mode FUNCTION OUTPUT PU/ PD
SM_D7 SM_ALE SM_CLE SM_nWP SM_nWPS GPIO14(SM_nCD) MS_BS MS_SCLK MS_D0 MS_D1 MS_D2 MS_D3 MS_D4 MS_D5 MS_D6 MS_D7 GPIO12(MS_INS) SD_CMD SD_CLK SD_D0 SD_D1 SD_D2 SD_D3 SD_D4 SD_D5 SD_D6 SD_D7 GPIO6(SD_WP)
SM SM SM SM SM GPIO MS MS MS MS MS MS MS MS MS MS GPIO SD SD SD SD SD SD SD SD SD SD GPIO
z z z z z z z z z z z z z z z z z z z z z z z z z z z 0
pd pd pd pd -pu pd pd pd pd pd pd pd pd pd pd pu ------------
-----yes ----------yes ------------
SM SM SM SM SM GPIO MS MS MS MS MS MS MS MS MS MS GPIO SD SD SD SD SD SD SD SD SD SD GPIO
hw hw hw (fw) z (fw) hw hw hw hw hw hw hw hw hw hw (fw) hw hw hw hw hw hw hw hw hw hw (fw)
pd pd pd pd pu (fw) hw hw pd hw pd pd pd hw pd pd (fw) pu -pu pu pu pu pu pu pu pu (fw)
yes ---yes (fw) --yes yes yes yes yes yes yes yes (fw) yes yes yes yes yes yes yes yes yes yes (fw)
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Table 6.1 USB2250/51/59 128-Pin Reset States (continued)
RESET STATE PIN NAME FUNCTION OUTPUT PU/ PD INPUT Post-Reset State xD Mode FUNCTION OUTPUT PU/ PD INPUT Post-Reset State SD Mode FUNCTION OUTPUT PU/ PD INPUT Post-Reset State MS Mode FUNCTION OUTPUT PU/ PD
GPIO15(SD_nCD) MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA13 MA16 MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 nMRD nMCE GPIO1(LED1) GPIO4 GPIO8/CARD_PWR0
GPIO MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA GPIO GPIO GPIO
z z z z z 0 0 0 0 0 0 0 0 0 0 z z z z z z z z 1 1 0 0 z
pu pd pd pd pd ----------pu pu pu pu pu pu pu pu ------
yes yes yes yes yes ------------------------
GPIO MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA MA GPIO GPIO GPIO
(fw) hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw hw 0 (fw) (fw) (fw)
(fw) --------------hw hw hw hw hw hw hw hw --(fw) (fw) (fw)
(fw) --------------hw hw hw hw hw hw hw hw --(fw) (fw) (fw) PWR VDD ---
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Table 6.1 USB2250/51/59 128-Pin Reset States (continued)
RESET STATE PIN NAME FUNCTION OUTPUT PU/ PD INPUT Post-Reset State xD Mode FUNCTION OUTPUT PU/ PD INPUT Post-Reset State SD Mode FUNCTION OUTPUT PU/ PD INPUT Post-Reset State MS Mode FUNCTION OUTPUT PU/ PD
GPIO9/CARD_PWR1 GPIO10/CARD_PWR2 GPIO11/CARD_PWR3 TEST nRESET MA12 MA14 MA15 nMWR GPIO3 GPIO5 SM_nRE SM_nWE SM_nB/R SM_nCE USB+ USBRBIAS XTAL1(CLKIN) XTAL2 REG_EN
GPIO GPIO GPIO TEST nRESET MA MA MA MA GPIO GPIO SM SM SM SM USB+ USB-
z z z z z 0 0 0 1 z 0 z z z z z z
----------pu -------
---yes yes ----yes --------
GPIO GPIO GPIO TEST nRESET MA MA MA MA GPIO GPIO SM SM SM SM USB+ USB-
(fw) (fw) (fw) z z hw hw hw hw (fw) (fw) hw hw z hw z z
(fw) (fw) (fw) ------(fw) (fw) (fw) (fw) (fw) (fw) hw hw
(fw) (fw) (fw) yes yes ----(fw) (fw) --yes -hw hw
PWR PWR PWR
VDD VDD VDD
----
----
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Chapter 7 DC Parameters
7.1 Maximum Guaranteed Ratings
SYMBOL TA MIN -55 150 325 VDD33, VDDA33 -0.5 -0.5 4.0 (3.3V supply voltage + 2) 6 MAX UNITS C C V V Soldering < 10 seconds COMMENTS
PARAMETER Storage Temperature Lead Temperature 3.3V supply voltage Voltage on USB+ and USB- pins Voltage on GPIO8, 9, 10 & 11
-0.5
VDD33 + 0.3
V
When internal power FET operation of these pins are enabled, these pins may be simultaneously shorted to ground or any voltage up to 3.63V indefinitely, without damage to the device as long as VDD33 and VDDA33 are less than 3.63V and TA is less than 70oC.
Voltage on any signal pin Voltage on XTAL1 Voltage on XTAL2 Note 7.1
-0.5 -0.5 -0.5
VDD33 + 0.3 4.0 VDD18 + 0.3
V V V
Stresses above the specified parameters may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used.
Note 7.2
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Voltage VDD33
tRT
3.3V 100%
90%
VSS
10%
t10%
Note 7.3
t90%
Time
Figure 7.1 Supply Rise Time Model When powering the device, the maximum power supply ramp time should be set at a rate faster than 400s. This speed is important to ensure that the device resets properly. Measure rise time at 10% and 90%.
7.2
Recommended Operating Conditions
PARAMETER SYMBOL TA VDD33, VDDA33 tRT 0 3.0 0 -0.3 MIN 70 3.6 400 5.5 MAX UNITS C V s V (Note 7.4) (See Figure 7.1 and Note 7.3) If any 3.3V supply voltage drops below 3.0V, then the MAX becomes: (3.3V supply voltage) + 0.5 5.5 COMMENTS
Operating Temperature 3.3V supply voltage 3.3V supply rise time Voltage on USB+ and USB- pins
Voltage on any signal pin Voltage on XTAL1 Voltage on XTAL2 Note 7.4
-0.3 -0.3 -0.3
VDD33 VDDA33 VDD18
V V V
A 3.3V regulator with an output tolerance of 1% must be used if the output of the internal power FET's must support a 5% tolerance.
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7.3
DC Electrical Characteristics
PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS
I, IPU, IPD Type Input Buffer Low Input Level High Input Level Pull Down Pull Up IS Type Input Buffer Low Input Level High Input Level Hysteresis ICLK Input Buffer Low Input Level High Input Level Input Leakage Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O12 Type Buffer Low Output Level VOL 0.4 V IOL = 12mA @ VDD33= 3.3V IOH = -12mA @ VDD33= 3.3V VIN = 0 to VDD33 (Note 7.5) IIL IIH -10 -10 +10 +10 A A VIN = 0 VIN = VDD33 VILCK VIHCK IIL 1.4 -10 +10 0.5 V V A VIN = 0 to VDD33 VILI VIHI VHYSI 2.0 420 0.8 V V mV TTL Levels VILI VIHI PD PU 2.0 72 58 0.8 V V A A TTL Levels
High Output Level
VOH
VDD33 - 0.4
V
Output Leakage
IOL
-10
+10
A
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PARAMETER I/O12, I/O12PU & I/O12PD Type Buffer Low Output Level
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL
0.4
V
IOL = 12mA @ VDD33= 3.3V IOH = -12mA @ VDD33= 3.3V VIN = 0 to VDD33 (Note 7.5)
High Output Level
VOH
VDD33 - 0.4
V
Output Leakage
IOL PD PU
-10
+10
A A A
Pull Down Pull Up IO-U (Note 7.6) I-R (Note 7.7) I/O200 Integrated Power FET for GPIO8, GPIO9, GPIO10, & GPIO11 High Output Current Mode Short Circuit Current Limit 200mA Low Output Current Mode Short Circuit Current Limit 100mA (Note 7.8) On Resistance (Note 7.8) Output Voltage Rise Time Supply Current Unconfigured Supply Current Active Full Speed High Speed Supply Current Standby Note 7.5 Note 7.6 Note 7.7 Note 7.8 Note 7.9
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72 58
IOUT ISC200 IOUT ISC100 RDSON tDSON ICCINIT ICC ICC ICSBY
200 TBD 100 TBD
mA mA mA mA s mA mA mA A
VdropFET = 0.46V VoutFET = 0V VdropFET = 0.23V VoutFET = 0V IFET = 70mA CLOAD = 10F
2.1
800 80 110 135 350 90 140 165 750
VDD, VDDP = 1.8V VDD33, VDDA = 3.3V
VDD, VDDP = 1.8V VDD33, VDDA = 3.3V
Output leakage is measured with the current pins in high impedance. See The USB 2.0 Specification, Chapter 7, for USB DC electrical characteristics RBIAS is a 3.3V tolerant analog pin. Output current range is controlled by program software. The assignment of each Integrated Card Power FET to a designated Card Connector is controlled by both firmware and the specific board implementation. Firmware will default to
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the settings listed in Table 10.1, "USB2250/51/59 GPIO Usage (ROM Rev 0x00)," on page 36. Note 7.10 The 3.3V supply should be at least at 75% of its operating condition before the 1.8V supply is allowed to ramp up.
7.4
Capacitance
TA = 25C; fc = 1MHz; VDD, VDDP = 1.8V Table 7.1 Pin Capacitance LIMITS PARAMETER SYMBOL CXTAL MIN TYP MAX 2 UNIT pF TEST CONDITION All pins (except USB pins and pins under test) are tied to AC ground.
Clock Input Capacitance
Input Capacitance Output Capacitance
CIN COUT
10 20
pF pF
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Chapter 8 AC Specifications
8.1 Oscillator/Clock
Crystal: Parallel Resonant, Fundamental Mode, 24 MHz 100ppm. External Clock: 50% Duty cycle 10%, 24/48 MHz 100ppm, Jitter < 100ps rms.
XTAL1 (C S1 = C B + C XTAL ) C1
Crystal
CL
1Meg
C2
XTAL2 (C S2 = C B + C XTAL )
Figure 8.1 Typical Crystal Circuit
Note: CB equals total board/trace capacitance.
(C1 + CS1) x (C2 + CS2) = CL (C1 + CS1 + C2 + CS2)
Figure 8.2 Formula to Find Value of C1 and C2
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Chapter 9 Package Outline
R EVISION HISTORY REVISION DESCRIPTION SEE SPEC F R T PAGE FOR REVI SIONHISTOR ON Y DATE REL EASED BY -
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Ultra Fast USB 2.0 Multi-Format Flash Media Controller
5
D D1 3
R1 R2 0.25
E1/4
GAUGE PLANE
0-7
3 E1 e
D 1/4
b 2
L E L1
4
DETAIL "A"
TOP VIEW
SEE DETAIL "A"
C A
SEAT ING PLANE
A2 c A1 ccc C
SIDE VIEW
NO T ES : 1. AL L D IM EN SION S AR E IN MIL LIME TE R. 2 . TR U E POSITION S PR EAD TOLE RA NC E OF EAC H L EA D IS 0 .0 3 5m m MAXIMU M. 3 . D IMEN SION S "D 1" A ND " E1 " DO N OT IN CL U DE M OLD PR OTRU SION S. M AX IMU M A LLOWED P ROTR U SIO N IS 0 .2 5 mm PER SIDE . 4 . D IME NSION "L" IS M EAS UR ED AT TH E GA UGE P LA NE , 0 .25 mm A BOVE TH E SEA TIN G P LAN E. 5 . D ETA IL S ON P IN 1 ID ENTIFIER ARE OPTIONA L BU T MU ST BE LOCA TED WITH IN TH E ZONE IN D IC ATE D.
UN LESS O H WISE SPEC T ER IFIED DIM SION AR IN MILLIMETERS EN SE AN TOLERANC ARE: D ES DECIMAL X.X 0.1 X.XX 0.05 X.XXX 0.025 AN GULAR 1 TH R ANG PROJ T ON ID LE EC I 80 ARKAY D RIVE H PPAUGE, N 11788 AU Y U SA
INTER PRET D AND T O PER IM L ASME Y14 M- 1994 .5 MATER IAL
TITLE NAME D RAW N D ATE
3-D VIEW
FINISH
S. K. ILI EV
C HECKED
12/17/04 12/17/04
PACKAGE OUTLINE 128 VTQFP-14x14x1.0mm BODY-0.4mm PITCH
DWG N UMBER R EV
PR T W IN ITH "SC ALE TO FIT" DO N SC OT ALE DR AWIN G
S. K. ILI EV
APPRO VED
MO-128-VTQFP-14x14x1.0
SC E AL STD C OMPLIAN E C SH EET
C 1 OF 1
S. K. ILI EV
12/17/04
1:1
JE DEC: MS -026 (D)
Figure 9.1 USB2250/51/59 128-Pin VTQFP, 14x14x1.0mm Body, 2.0mm Pitch
Ultra Fast USB 2.0 Multi-Format Flash Media Controller Datasheet
Chapter 10 GPIO Usage
Table 10.1 USB2250/51/59 GPIO Usage (ROM Rev 0x00) NAME GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16-32 ACTIVE LEVEL H H H H H L H L L L L L L L L USER LED1 CF_DMARQ / RXD VBUS_DET SCL / xD_ID SDA SD_WP CF_nDMACK / TXD CRD_PWR0 CRD_PWR1 CRD_PWR2 CRD_PWR3 MS_INS CF_nCD xD_nCD SD_nCD GPIO [32:16] SYMBOL DESCRIPTION AND NOTE LED indicator Compact Flash DMA request / Receive Port of Debugger USB Vbus detect Serial EEPROM clock output / xD card detect Serial EEPROM data SD Write Protect Compact Flash DMA acknowledge / Transmit Port of Debugger Card Power Control Card Power Control Card Power Control Card Power Control Memory Stick Card Insertion Compact Flash card detect xD card detect Secure Digital card detect User defined
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